Product Summary

The CD54HC374F3A is a high-speed CMOS logic octal D-Type flip-flop, 3-State Positive-Edge Triggered and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the LOWto HIGH transition of clock (CP). The output enable (OE) controls the 3-state outputs and is independent of the register operation. When OE is HIGH, the outputs are in the high-impedance state. The CD54HC374F3A is identical in function and differ only in their pinout arrangements.

Parametrics

CD54HC374F3A absolute maximum ratings: (1)DC Supply Voltage, VCC: -0.5V to 7V; (2)DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V: ±20mA; (3)DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V: ±20mA; (4)DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V: ±35mA; (5)DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V: ±25mA; (6)DC VCC or Ground Current, ICC: ±50mA.

Features

CD54HC374F3A features: (1)Buffered Inputs; (2)Common Three-State Output Enable Control; (3)Three-State Outputs; (4)Bus Line Driving Capability; (5)Typical Propagation Delay (Clock to Q) = 15ns at VCC = 5V, CL = 15pF, TA = 25oC; (6)Fanout (Over Temperature Range), Standard Outputs: 10 LSTTL Loads; Bus Driver Outputs: 15 LSTTL Loads; (7)Wide Operating Temperature Range:-55℃ to 125℃; (8)Balanced Propagation Delay and Transition Times; (9)Significant Power Reduction Compared to LSTTL Logic ICs; (10)HC Types, 2-V to 6-V Operation; High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V; (11)HCT Types, 4.5-V to 5.5-V Operation; Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min); CMOS Input Compatibility, Il . 1μA at VOL, VOH.

Diagrams

CD54HC374F3A block diagram

CD54
CD54

Other


Data Sheet

Negotiable 
CD54/74HC161
CD54/74HC161

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CD54/74HC163
CD54/74HC163

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CD54/74HC192
CD54/74HC192

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CD54/74HC193
CD54/74HC193

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Data Sheet

Negotiable 
CD54/74HC240
CD54/74HC240

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Data Sheet

Negotiable